Logic Level Converter

Precision voltage translation for 5V, 3.3V, 2.5V, 1.8V systems. Computes resistor divider values with optional load impedance, estimates maximum signal frequency, and verifies logic family compatibility (VIH/VIL and overvoltage). Includes E24/E96 series recommendations, circuit diagrams, and design notes for unidirectional level shifting.

High-level voltage from driver
Required logic high at receiver
Fixed top resistor (optional)
Fixed bottom resistor (optional)
Receiver input resistance. Use 1000+ for high impedance.
Affects rise time & maximum frequency.
5V → 3.3V (classic)
3.3V → 1.8V (FPGA/CPLD)
5V → 2.5V (ADC reference)
1:1 Ratio test
12V → 5V (logic gate protection)
Privacy-first design: All calculations are performed locally in your browser. No data is transmitted or stored.
Vsrc (Input)
Vout (Output)
Resistors R1, R2

Logic Family Compatibility Checker (with overvoltage protection)

Logic Family Compatibility Checker

Advanced Design Guidelines for Resistive Level Shifters

Interfacing between different voltage domains is routine in mixed-signal systems. A resistive voltage divider is the simplest unidirectional level shifter for slow signals (GPIO, reset lines, status LEDs). However, to achieve reliable operation, engineers must account for load impedance, signal frequency, and input capacitance. This calculator incorporates these factors to provide realistic design recommendations.

Loaded voltage divider equation:
Vout = Vsrc × (R2 ∥ Rload) / (R1 + (R2 ∥ Rload))
Where R2 ∥ Rload = (R2 × Rload) / (R2 + Rload).
Maximum frequency (RC limited): fmax ≈ 1 / (2π × Req × Cload), with Req = R1 ∥ (R2+Rload) for falling edge, or simply R1+R2 for charging? Practical estimation uses the Thevenin resistance seen by the load capacitance.

When to Avoid a Resistive Divider

  • Bidirectional signals (I2C, SMBus) require a MOSFET-based shifter (e.g., BSS138).
  • High speed (>1 MHz) or high capacitive load >50 pF: rise time degrades, causing logic errors.
  • Low receiver input impedance (< 10 kΩ): loading reduces Vout significantly; use a buffer or active translator.
  • Overvoltage risk: If Vsrc exceeds the receiver's absolute maximum rating, a resistive divider may not protect against transients — use clamping diodes or a dedicated translator.

Step-by-Step Design with Load Consideration

  1. Measure or estimate the receiver's input resistance (Rload) and capacitance (Cload). Typical CMOS inputs: 1 MΩ // 5-15 pF.
  2. Enter Vsrc, Vtarget, and load parameters into the tool.
  3. Optionally fix R1 or R2, or let the tool auto-select using preferred E-series values.
  4. Verify the loaded Vout is at least 90% of the receiver's VIH (including tolerance).
  5. Check the estimated maximum frequency — if too low, reduce resistor values (trade-off with power).
Real‑world case: 5V Arduino to 3.3V sensor with long cable

A 5V microcontroller driving a 3.3V SPI sensor over 30 cm of ribbon cable (Cload ≈ 50 pF). Using the classic 10k/19.6k divider, the tool calculates Req ≈ 6.7 kΩ, leading to rise time ≈ 2.2 × Req × Cload = 737 ns, limiting data rate to ~500 kHz. By reducing resistors to 2.2k/4.3k, rise time drops to 160 ns, allowing 3 MHz operation. The calculator helps identify this trade-off.

Frequency and Rise Time Estimation

For a divider, the output rise time (10% to 90%) is approximated by τ = 2.2 × Rth × Cload, where Rth = R1 ∥ (R2 + Rsrc) and Rsrc is the driver output resistance (≈ 25 Ω). The maximum practical square wave frequency is roughly 0.35 / tr (bandwidth rule). The tool provides a conservative estimate to avoid signal integrity issues.

Logic family VOH min (V) VIH min (V) VOL max (V) VIL max (V) Abs max Vin (V)
5V TTL 2.4 2.0 0.4 0.8 5.5
5V CMOS 4.7 3.5 0.5 1.5 5.5
3.3V LVTTL 2.4 2.0 0.4 0.8 3.6
3.3V LVCMOS 3.0 2.0 0.4 0.9 3.6
1.8V CMOS 1.6 1.2 0.45 0.6 1.98

Engineering authority — This tool references TI Logic Guide 2024, NXP I2C level shifting app note (AN10441), and The Art of Electronics (Horowitz & Hill, 3rd ed.). Resistor values comply with IEC 60063. All calculations consider load effects per standard circuit theory. Always verify with component datasheets.

References: TI Level Shifting Techniques | NXP I2C Bidirectional Level Shifter | Analog Devices: I2C Level Translation

Frequently Asked Questions

The receiver's input resistance acts as a parallel resistor to R2, reducing the effective bottom resistance. The calculator accounts for this. If the loaded Vout is too low, decrease R1 and R2 proportionally or use a buffer.

The tool estimates the RC-limited rise time. For clean digital signals, the maximum frequency is roughly 0.35 / rise_time. If your required frequency exceeds the estimate, reduce resistor values (but power will increase).

No — I2C requires open-drain bidirectional operation. Use a dedicated MOSFET level shifter (e.g., BSS138 module). The resistive divider will block low-level signals from the slave side.

The compatibility checker will flag an overvoltage risk. Even if the divider lowers the nominal voltage, transients or startup conditions might exceed the absolute rating. Use a dedicated level translator with overvoltage protection or a series resistor plus Zener clamp.

Because the loaded output voltage depends on R2 in parallel with Rload. The tool compensates by increasing R2 to maintain the target Vout under load.

For a short PCB trace and a single CMOS input: 5-15 pF. For a cable or multiple inputs: 30-100 pF. When in doubt, measure or use 50 pF as a conservative estimate.