Calculate output voltage, input voltage, or resistor values in a classic two‑resistor divider. Includes visual circuit schematic, loading effect notes, and step‑by‑step derivation.
A voltage divider is a passive linear circuit that produces an output voltage (Vout) that is a fraction of its input voltage (Vin). It consists of two resistors connected in series across a voltage source. The fundamental formula is derived from Kirchhoff’s voltage law and Ohm’s law:
This relationship is linear and widely used in sensor networks, potentiometer circuits, reference voltages, analog-to-digital converter (ADC) inputs, and level shifting. Unlike a voltage regulator, a resistive divider is unregulated – the output voltage changes if the load current varies.
Current flowing through both resistors: I = Vin / (R1+R2). Then Vout = I·R2 = Vin·R2/(R1+R2). To find R1 given Vout, Vin, R2: R1 = R2·(Vin/Vout - 1). Similarly, R2 = R1·(Vout/(Vin-Vout)).
| Desired ratio | Resistor selection (R1/R2) | Typical application |
|---|---|---|
| 0.5 (half) | R1 = R2 | Bias voltage, virtual ground |
| 0.333 (1/3) | R1 = 2·R2 | Step-down for 12V → 4V |
| 0.1 (10:1) | R1 = 9·R2 | Oscilloscope probe compensation |
| 0.833 (5/6) | R1 = R2/5 | Level shifting from 5V to 4.17V |
In real circuits, the load (e.g., ADC input, op‑amp) connected to Vout draws current, which reduces the output voltage. The effective output impedance of the divider is R1||R2 (parallel combination). To minimize loading error, ensure the load impedance is at least 10× higher than the divider’s Thevenin resistance. For precision applications, use a unity‑gain buffer (op‑amp voltage follower). This calculator computes the ideal no‑load voltage; we include the parallel resistance as an indicator.
Power dissipation: The total current through the divider is \(I = V_{in}/(R_1+R_2)\). Power in each resistor is \(I^2R\). For reliable operation, choose resistors rated for at least twice the calculated dissipation (e.g., 0.25 W for most signal‑level dividers). Excessive power can cause thermal drift or permanent damage. Example: a 12 V divider with R1+R2 = 1 kΩ draws 12 mA and dissipates 144 mW – a standard 0.25 W resistor is adequate, but 0805 SMD may run hot.
An ESP32 ADC reads a lithium battery (max 4.2V) but the ADC absolute maximum is 3.3V. Using a voltage divider: Vout,max = 3.3V, Vin = 4.2V ⇒ ratio = 3.3/4.2 ≈ 0.7857. Choose R1 = 10kΩ, then R2 = R1·(Vout)/(Vin-Vout) = 10k·3.3/(4.2-3.3)=10k·3.667≈36.67kΩ (use 36kΩ standard). This calculator quickly validates the exact values and warns about equivalent Thevenin resistance (≈7.9kΩ) which is acceptable for high‑impedance ADC (10‑12 bit).
Worst‑case tolerance analysis: With 5% resistors, R1 = 10 kΩ ±5% (9.5 kΩ to 10.5 kΩ) and R2 = 36 kΩ ±5% (34.2 kΩ to 37.8 kΩ). The resulting Vout can vary between 3.03 V and 3.58 V – a ±8% error. For critical ADC references, prefer 1% resistors or use a precision voltage reference.
Resistors are manufactured in preferred numbers (E12, E24, E96 series). The calculated values may not be standard; we recommend selecting the nearest standard value and recalculating error. E‑series: E12 (10,12,15,18,22,27,33,39,47,56,68,82) multiplied by powers of 10. For high precision, use E96 (1% tolerance). This tool is ideal for rapid prototyping before BOM selection.
Example: If the calculator returns R2 = 47.3 kΩ, the nearest E24 value is 47 kΩ (error ≈ 0.6%). For 1% precision, use E96 (47.5 kΩ). You can recalculate Vout with the substituted standard value to verify the deviation.
The divider’s Thevenin resistance Rth = R1||R2 = (R1·R2)/(R1+R2). For AC signals, parasitic capacitance across R2 creates a low‑pass filter with cutoff frequency fc = 1/(2π·Rth·Cload). In high‑speed designs, this limits bandwidth. The calculator shows Rth for reference. When working with high frequencies, prefer lower resistor values (hundreds of ohms to few kΩ) to reduce RC time constant.